The present invention disclosed herein relates to semiconductor memories and more particularly, to an apparatus and method for controlling a test mode of a semiconductor memory.
With an increase of memory capacity, a general semiconductor memory usually employs multi-bank architecture with 2, 4, or 8 banks to efficiently control its entire memory area.
In a conventional semiconductor memory, a normal operation mode only operates with one of the banks, but a test mode (e.g., a parallel test mode) is operable with all of the banks arranged therein and by test apparatus connected thereto.
For example, a semiconductor memory with a 4-bank architecture, as shown in FIG. 1, includes first through fourth banks BK0-BK3, and eight pads 20 from 0 to 7 in numeric order. Two pads 20 are allocated to each of the first through fourth banks BK0-BK3 as shown in FIG. 1.
Such a semiconductor memory, structured as illustrated in FIG. 1, is put into a test operation on test apparatus (not shown), as follows.
The test apparatus first inputs a predetermined address into semiconductor memory for conducting the test mode.
The semiconductor memory sets its operation mode as the test mode by decoding the address.
In this case of setting the test mode, the semiconductor memory activates all of the first through fourth banks BK0-BK3 to output data by way of the pads 20.
Namely, as shown in FIG. 2, even and odd data, Q0/Q2 and Q1/Q3, are sequentially output by the pads 20 allocated to each of the banks BK0-BK3.
Thereby, the test apparatus tests the operational state of the semiconductor memory with the data output through the pads 20.
On the other hand, a semiconductor memory with an 8-bank architecture, as shown in FIG. 3, includes first through eighth banks BK0-BK7 and 16 pads 30.
In the semiconductor memory with the 8-bank architecture, a test mode is carried out for the first group of four banks BK0-BK3 using the first through seventh pads (0-7 or 8-15 in numeric order) and next for the second group of four banks BK4-BK7 using the unit of the eight pads (0-7 or 8-15 in numeric order).
However, such conventional test schemes have the disadvantages outlined as follows.
First, since the plurality of banks are adjacent to each other and activated at the same time during the test mode, it causes many fluctuations different from a practical operation of the semiconductor memory, such as noises due to a rapid increase of power consumption. This creates data output errors thereby preventing a reliable test operation from taking place.
Second, as pads in a separate location are used in the semiconductor memory with the 8-bank architecture during the test mode, complex hardware and software configurations in the test equipment, as well as modifications to the hardware and software structure therein are required.